1. Field of the Invention
Example embodiments of the present invention relate to a method of forming a nanowire and a method of manufacturing a semiconductor device using the same. More particularly, example embodiments of the present invention relate to a method of forming a nanowire including a semiconductor material by using a bulk semiconductor substrate, and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
As information process apparatuses, such as computers, have been widely used, semiconductor devices employed in the information process apparatuses have also been rapidly developed to have high response speeds and large storage capacities. Thus, semiconductor manufacturing technology has been developed to improve the integration degree, the reliability and the response speed of the semiconductor device.
Since a metal oxide semiconductor (MOS) transistor is a main component in a current semiconductor memory device, the MOS transistor is required to have low power consumption, a high integration degree, a rapid response speed, etc. To improve characteristics of a conventional MOS transistor, a channel length of the MOS transistor is reduced and depths of source/drain regions in the MOS transistor are decreased. In addition, a gate insulation layer of the MOS transistor has a reduced effective thickness.
However, the MOS transistor may have degraded electrical characteristics because of a short channel effect caused by the decrease of the channel length. Additionally, the MOS transistor may have an increased contact resistance when the source/drain regions have the reduced depths. Furthermore, the gate insulation layer may not have a desired thickness because of the current semiconductor manufacturing technology. Hence, the conventional MOS transistor may not meet desired high-speed operation characteristics.
A planar type transistor has a channel region adjacent to a surface portion of a semiconductor substrate. Thus, surface scattering of electrons may be caused when the electrons are moved through the channel region of the planar type transistor. As a result, mobility of the electrons may be considerably reduced so that the planar type transistor may not have the required high response speed.
Recently, a semiconductor nanowire has been employed as a channel of a transistor so as to obtain the transistor having a low power consumption, a high integration degree, a rapid response speed, etc. The semiconductor nanowire indicates a wire having a width of several nanometers to scores of nanometers.
However, the nano-technology for manufacturing the transistor has not yet been sufficiently developed because a nano-sized semiconductor material shows electrical, chemical and optical characteristics quite different from those of a bulk semiconductor material due to the high ratio of the surface area relative to the volume in the nano-sized semiconductor material and the quantum bonding effect of the nano-sized semiconductor material.
A carbon nanotube (CNT) has been mainly researched as a nano-sized semiconductor material in a semiconductor device. For example, the CNT is used as a channel of a field effect transistor (FET). However, the CNT may have poor characteristics for a channel in a semiconductor device such as a transistor, because the electrical conductivity and band gap of the CNT may not be properly adjusted.
Recently, besides the CNT, various nano-sized semiconductor materials have been researched to form a semiconductor nanowire in a semiconductor device such as a transistor. For example, a semiconductor nanowire of silicon has an excellent crystalline structure so that the semiconductor nanowire of silicon may be directly employed as a channel of the transistor. Further, the electrical conductivity and band gap of the semiconductor nanowire may be adjusted by doping impurities therein.
Particularly, a volume inversion may be generated in a semiconductor nanowire when the semiconductor nanowire is employed in a channel of a transistor, and a gate of the transistor completely encloses the semiconductor nanowire. Thus, electrons may move through the semiconductor nanowire without surface scattering thereof, and the mobility of the electrons may increase, thereby improving the response speed of the transistor. Further, the short channel effect may not occur in the transistor including the semiconductor nanowire.
A conventional semiconductor nanowire is usually formed by growing a semiconductor material through a selective epitaxial growth (SEG) process. When the conventional semiconductor nanowire is formed by the SEG process, however, manufacturing processes are complicated and manufacturing costs may increase. Further, the electrical characteristics of the conventional nanowires may not be constantly maintained through the SEG process.
Therefore, a more simple method is still required to form a semiconductor nanowire with low cost.